Generally, current drivability required in biasing semiconductor substrate (or well formed at semiconductor substrate) by charge pump circuit for substrate bias must be equal to value in which margin is added to substrate current. It is considered that the main cause of the substrate current is due to collision ionization taking place as the result of the fact that electrons flowing between the source and the drain of MOS transistor are accelerated by high electric field. Moreover, reverse bias leakage current of PN junction within the device is added in addition to the above. Empirically, as seen from the actual measurement result shown in FIGS. 6 and 7, with respect to substrate current I.sub.sub, the following equations (1), (2) hold between the source-drain voltage V.sub.DS and the drain current. EQU ln I.sub.sub .alpha.-1/V.sub.DS ( 1) EQU I.sub.sub .alpha.I.sub.D ( 2)
When the substrate bias is caused to be large by the charge pump circuit for substrate bias, the substrate current is also decreased in accordance with to what degree the drain current is decreased by the back-gate effect. Accordingly, as the current drivability of the charge pump circuit, it is required for the current drivability of the charge pump circuit that this charge pump circuit can be driven by the maximum substrate current when the substrate bias at the time of start of driving is zero V.
A charge pump circuit used for biasing the P-type substrate or the P-well is shown in FIG. 8. This charge pump circuit includes four P-channel MOS transistors M.sub.0, M.sub.1, M.sub.2, M.sub.3 connected in series, and capacitors C.sub.1, C.sub.2, C.sub.3, and is driven by two clocks CLK1, CLK2 which are the same in frequency, but are shifted in phase.
Gates of respective transistors M.sub.0, M.sub.1, M.sub.2, M.sub.3 are respectively connected to their own drains. Drain of transistor M.sub.0 is connected to ground power supply terminal GND, and source of transistor M.sub.3 is connected to P-type substrate or P-well. In addition, for each positive integer i from 1 to 3, one end of capacitor C.sub.i is connected to gate of the transistor M.sub.i.
Further, clock CLK1 is applied to the other ends of the capacitors C.sub.1, C.sub.3, and clock CLK2 is applied to the other end of capacitor C.sub.2.
The operation of this charge pump circuit will now be described. When positive pulse is applied to the capacitors C.sub.1, C.sub.3 as clock CLK1, potentials of node N.sub.1 (gate and drain of transistor M.sub.1) and of node N.sub.3 (gate and drain of transistor M.sub.3) rise in response to rising of this pulse. As a result, gate-source voltages V.sub.GS of transistors M.sub.0, M.sub.2 are above the threshold voltage V.sub.th so that they are turned ON. Thus, electrical charges stored in the capacitors C.sub.1, C.sub.3 are transferred to ground power supply GND and capacitor C.sub.2 through the transistors M.sub.0, M.sub.2. By this transfer of electrical charges, potentials on the nodes N.sub.1, N.sub.3 shortly return to original potential. As a result, gate-source voltages V.sub.GS of transistors M.sub.0, M.sub.2 are below the threshold voltage so that they are turned OFF.
Moreover, when the pulse falls down, potentials of the nodes N.sub.1, N.sub.3 are lowered. As a result, gate-source voltages V.sub.GS of the transistors M.sub.1, M.sub.3 are above the threshold voltage V.sub.th so that they are turned ON. Thus, electrical charges stored in the capacitor C.sub.2 and the substrate (or well) are transferred to the capacitors C.sub.1, C.sub.3 through the transistors M.sub.1, M.sub.3. By transfer of these electrical charges, potentials of the nodes N.sub.1, N.sub.3 shortly return to original potential. Thus, gate-source voltages V.sub.GS of the transistors M.sub.1, M.sub.3 are below the threshold voltage V.sub.th so that they are turned OFF.
When positive pulse is applied to the capacitor C.sub.2 as clock CLK2, potential of the node N.sub.2 rises in response to rising of this pulse. As a result, gate-source voltage V.sub.GS of the transistor M.sub.1 is above the threshold voltage V.sub.th so that it is turned ON. Thus, electrical charges stored in the capacitor C.sub.2 are transferred to the capacitor C.sub.1 through the transistor M.sub.1. By transfer of these electrical charges, potential of the node N.sub.2 shortly returns to original potential. Thus, the gate-source voltage V.sub.GS of the transistor M.sub.1 is below the threshold voltage V.sub.th so that it is turned OFF.
By repeating an operation as described above, electrical charges of the P-type substrate (or P-well) are carried in a manner of bucket relay through the capacitors C.sub.1, C.sub.2, C.sub.3 and are sent into ground power supply GND. Thus, potential of the P-type substrate (or P well) gradually falls.
The current drivability I.sub.pump of such charge pump is represented by the following equation. EQU I.sub.pump =f.sub.CLK .multidot.C.multidot.(V.sub.CLK -V.sub.th)(3)
In the above-mentioned equation, f.sub.CLK is frequency of clocks CLK1, CLK2, C is capacitance of the capacitors C1, C2, C3, V.sub.CLK is clock amplitude, and V.sub.th is threshold voltage of MOS transistor.
Moreover, when n is the number of stages of transistors connected in series, the maximum arrival voltage V.sub.pump that the substrate bias V.sub.SUB can arrive by this charge pump is represented by the following equation. EQU V.sub.pump =(n-1).multidot.V.sub.CLK -n.multidot.V.sub.th ( 4)
The substrate on which the MOS transistors M.sub.0, M.sub.1, M.sub.2, M.sub.3 constituting the above-described charge pump circuit are formed is connected to the terminal of power supply voltage V.sub.DD (=3.3 V), and source potential of the transistor M.sub.0 is 0V+V.sub.th. Accordingly, there results the state where back-gate voltage of (3.3V-V.sub.th) is applied.
Moreover, with respect to source potentials of the transistors M.sub.1, M.sub.2, M.sub.3, according as potential of the substrate (or well) is lowered to more degree by action of the charge pump circuit, back-gate voltage is applied to more degree. For this reason, the threshold voltage becomes large for back-gate effect.
The simulation result of the current drivability characteristic with respect to output voltage of the above-described charge pump circuit is shown in FIG. 9. The maximum arrivable voltage of the substrate bias is determined by the number of stages of transistors connected in series as seen from the equation (4), and the current drivability is substantially constant until output voltage becomes close to the maximum arrival voltage as seen from the simulation result of FIG. 9.
Accordingly, in the conventional semiconductor integrated circuit device having such charge pump circuit, in the case where the number of stages of transistors connected in series is increased for the purpose of increasing the maximum arrival voltage, it is required to prepare capacitors C.sub.1, C.sub.2, C.sub.3 of large capacity, etc. caused to be in correspondence with the maximum substrate current when the substrate bias at the time of starting of drive which is required as the current drivability of the charge pump circuit is zero V by the number corresponding to the number of the capacitors C.sub.1, C.sub.2, C.sub.3, etc. This means increased chip area.
In addition, the power supply voltage has a tendency to be lowered in future. Since the clock amplitude V.sub.CLK also becomes small followed by this, it is required to increase the number n of stages of transistors connected in series in order to allow the arrival voltage shown in the equation (4) to be unchanged. This results in increased number of capacitors, giving rise to the problem of increase in the device area, i.e., increase in the chip area.